Design

Rianta Solutions provides specialized ASIC/SoC Intellectual Property(IP) and Engineering Services for Datacenter Infrastructure, Communications Infrastructure, and Automotive Networking.

Our typical engagement with ASIC/SoC customers is a project level offering that includes Engineering Design, Verification Services and Physical Design along with ASIC/SoC IP Core and Verification IP(VIP) Products . We can also provide a full UVM verification environment that can be integrated with the customer’s sub-system or chip level environments. Our software engineering team can also offer software IP and APIs for device drivers and SDKs in order to configure and manage the underlying Rianta IP blocks.

ASIC/SoC Design Services

Rianta’s ASIC, SoC, ASSP, and FPGA design service experts can work as part of your team, providing specialized services, or we can take full ownership of a complete turnkey project. We have engagement models to suit your needs, including fixed price and time & materials options.

Rianta offers the following ASIC/SoC Design Services:

Top Level Design and Simulation

Specification, Architecture, Design Partitioning, RTL Coding Verilog/VHDL
Technology Selection, Subsystem and System Integration and Debug
- Qualify and integrate 3rd party IP, Deep Domain expertise with multiple vendors
Subsystem interconnect ( coherent, non-coherent (e.g AMBA))
Design, Optimization, Modeling, Performance Analysis/Engineering :
- Multicore Processing, Caching, Virtualization, Fabrics, DMA
- Deep Learning Accelerator subsystems
- IO throughput, Latency, bus utilization, on-chip memory efficiency
- Security and Compression Acceleration
Design for reuse, multi-project design databases
Deep Learning Acceleration Design and Optimization for Training and Inference
- State of the art algorithm, architecture application analysis, (Natural Language Processing, RNN, CNN, LSTM, Resnet, Alexnet, Image and Video processing)
- Matrix Multiplication, Convolution, Vector Processing, Non Linear Functions
- Algorithm Design and Optimization to leverage hardware acceleration capabilities
High Speed Deep Learning Data Management and Delivery Systems
- Distributed on-chip memory
- Inter/intra processing engine data highway
- Multi-dimensional data DMA
Power and Gate Count reduction strategies
Simulation using leading EDA tools
ECOs for last minute feature changes and timing closure
Project Management, Bug/Issue Trackers, Time Trackers, Revision Control
Automated Design and Verification using Rianta Tools

Synthesis, Timing Closure and Timing Analysis

Synthesis with Synopsys and Cadence EDA tools
Timing analysis and closure
Tcl, Perl scripting for constraint generation, synthesis and analysis
Low power optimization

Design for Testability

Scan, BIST, JTAG insertion and verification
Test wrapper creation for 3rd party IP Cores
ATPG vector generation, conversion and verification
Design for Debug
Built-In pattern generators and analyzers for lab, field and manufacturing test

ASIC/SoC Integration and Verification

Integration of 3rd Party IP and Rianta IP Core Products
Top level and 3rd Party IP Core verification
Deep Learning Algorithm Design, Optimization, Validation, Verification, Modeling, Integration with ML frameworks (e.g. Tensorflow, PyTorch)
System level Use case analysis and validation
SW Co-Sim/validation on HW emulation platform

Physical Design Services

Large hierarchical designs
Low power design techniques
RTL2GDSII
Floorplanning (Full Chip Hierarchical and Block Level)
Power Grid Design and Optimization
Place & Route (PNR)
Clock Tree Synthesis (CTS) and Clock Mesh
Static Timing Analysis (STA) and Extraction
Timing Closure
Physical Verification (LVS, DRC)
Design for Test (DFT)
Electro Migration(EM) and IR Drop Analysis
Experience with multiple vendor tool flows
IP Integration expertise
Perl and TCL Scripting languages
Advanced Geometries experience with leading factories